JPS60182596A - 半導体記憶回路 - Google Patents

半導体記憶回路

Info

Publication number
JPS60182596A
JPS60182596A JP59250665A JP25066584A JPS60182596A JP S60182596 A JPS60182596 A JP S60182596A JP 59250665 A JP59250665 A JP 59250665A JP 25066584 A JP25066584 A JP 25066584A JP S60182596 A JPS60182596 A JP S60182596A
Authority
JP
Japan
Prior art keywords
circuit
node
gate
memory
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59250665A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0217875B2 (en]
Inventor
マーチン・デニス・モイニハン
トーマス・アルバート・ウイリアムズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS60182596A publication Critical patent/JPS60182596A/ja
Publication of JPH0217875B2 publication Critical patent/JPH0217875B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Landscapes

  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
JP59250665A 1984-02-27 1984-11-29 半導体記憶回路 Granted JPS60182596A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/584,033 US4584669A (en) 1984-02-27 1984-02-27 Memory cell with latent image capabilities
US584033 1996-01-11

Publications (2)

Publication Number Publication Date
JPS60182596A true JPS60182596A (ja) 1985-09-18
JPH0217875B2 JPH0217875B2 (en]) 1990-04-23

Family

ID=24335628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59250665A Granted JPS60182596A (ja) 1984-02-27 1984-11-29 半導体記憶回路

Country Status (3)

Country Link
US (1) US4584669A (en])
EP (1) EP0156135A3 (en])
JP (1) JPS60182596A (en])

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008128165A (ja) * 2006-11-24 2008-06-05 Mitsubishi Electric Corp ヒートポンプ装置

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855803A (en) * 1985-09-02 1989-08-08 Ricoh Company, Ltd. Selectively definable semiconductor device
JP2588936B2 (ja) * 1988-07-04 1997-03-12 沖電気工業株式会社 半導体記憶装置
US4995004A (en) * 1989-05-15 1991-02-19 Dallas Semiconductor Corporation RAM/ROM hybrid memory architecture
US5517634A (en) * 1992-06-23 1996-05-14 Quantum Corporation Disk drive system including a DRAM array and associated method for programming initial information into the array
US5455788A (en) * 1993-08-24 1995-10-03 Honeywell Inc. SRAM to ROM programming connections to avoid parasitic devices and electrical overstress sensitivity
US5426614A (en) * 1994-01-13 1995-06-20 Texas Instruments Incorporated Memory cell with programmable antifuse technology
US5986962A (en) * 1998-07-23 1999-11-16 International Business Machines Corporation Internal shadow latch
US6122216A (en) * 1998-12-09 2000-09-19 Compaq Computer Corporation Single package dual memory device
CN103959424B (zh) * 2011-12-06 2017-07-18 皇家飞利浦有限公司 旋转阳极的平衡
US9202554B2 (en) 2014-03-13 2015-12-01 International Business Machines Corporation Methods and circuits for generating physically unclonable function

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3493786A (en) * 1967-05-02 1970-02-03 Rca Corp Unbalanced memory cell
US3634929A (en) * 1968-11-02 1972-01-18 Tokyo Shibaura Electric Co Method of manufacturing semiconductor integrated circuits
US3662351A (en) * 1970-03-30 1972-05-09 Ibm Alterable-latent image monolithic memory
DE2165729C3 (de) * 1971-12-30 1975-02-13 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithische, als Lese/Schreiboder als Festwertspeicher betreibbare Speicheranordnung
US3764825A (en) * 1972-01-10 1973-10-09 R Stewart Active element memory
US3755793A (en) * 1972-04-13 1973-08-28 Ibm Latent image memory with single-device cells of two types
US3820086A (en) * 1972-05-01 1974-06-25 Ibm Read only memory(rom)superimposed on read/write memory(ram)
US4175290A (en) * 1977-07-28 1979-11-20 Hughes Aircraft Company Integrated semiconductor memory array having improved logic latch circuitry
US4149268A (en) * 1977-08-09 1979-04-10 Harris Corporation Dual function memory
US4278897A (en) * 1978-12-28 1981-07-14 Fujitsu Limited Large scale semiconductor integrated circuit device
US4418401A (en) * 1982-12-29 1983-11-29 Ibm Corporation Latent image ram cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008128165A (ja) * 2006-11-24 2008-06-05 Mitsubishi Electric Corp ヒートポンプ装置

Also Published As

Publication number Publication date
JPH0217875B2 (en]) 1990-04-23
US4584669A (en) 1986-04-22
EP0156135A2 (en) 1985-10-02
EP0156135A3 (en) 1987-09-23

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